1. Field of the invention
The present invention concerns a read/write memory cell and a read/write memory obtained by association of such cells, more particularly implemented in integrated circuit form, especially in semi-custom integrated circuit form.
2. Description of the prior art
A semi-custom integrated circuit is a set of transistors, of the MOS type, for example, fabricated in advance on a common semiconductor substrate according to a regular structure which is independent of the function to be subsequently implemented by the integrated circuit, and which are subsequently interconnected to order, as appropriate to the type of function to be implemented by the integrated circuit, a number of areas reserved for interconnections being to this end provided on the surface of the integrated circuit.
The advantage of this technique is to concentrate in the final stage of the fabrication process the implementation of the "customized" part of the integrated circuit, namely the interconnections, and to relegate to preceding stages implementation of the "standard" part of the integrated circuit, common to all users.
On the other hand, it has the disadvantage of making the implementation of the interconnections very complicated beyond a certain degree of complexity of the function to be implemented. As the transistors are disposed in parallel rows, the interconnections consist of a network essentially disposed between these rows (there are in fact a number of interconnections within the rows themselves).
It will be readily appreciated that the number of possibilities is extremely high, given the architecture and the type of function to be implemented, which is hardly consistent with the extreme rigidity of the structure as described.
A well known consequence of this contradiction between the multiplicity of the interconnections of a circuit and the surface area assigned to these interconnections (non-modifiable surface area) is that manufacturers of integrated circuits recommend that a number of transistors (20% in relatively simple situations) remain unused to facilitate the routing of the interconnections. According to the relative complexity of the functions to be implemented, there is thus observed in certain cases a loss of yield of the circuits in terms of surface area used or the converse problem of difficulties in realising the interconnection diagram (when the interconnection network is very dense) and a significant loss of time for its implementation. In certain cases the difficulty may be so great that the integrated circuit manufacturers are obliged to modify the "standard" part of the circuit to provide more space for the areas reserved for interconnections, resulting of course in a loss of yield for all users, that is to say whatever the function to be implemented.
French patent application No 82 05245 filed Mar. 26, 1982 proposes a solution to this problem which consists in providing a continuous succession of rows of transistors over the entire surface area of the substrate and, where necessary, using the surface area occupied by certain of these rows, which are then not connected to the power supply, to make horizontal interconnections (assuming the rows of transistors are horizontal). To obtain a complete interconnection network, vertical interconnections may then be made on an insulative layer covering the horizontal interconnections.
This latter technique corresponds to the so-called free interconnection semi-custom integrated circuit technique.
The present invention is more particularly concerned with the implementation of read/write memories (also known as random access memories) in integrated circuit form. These are not for main memory purposes (for which commercially available high-capacity devices are without doubt a better solution), but rather decentralized memories for specific peripheral processing tasks. In this case the use of standard commercially available memories results in a very low yield since the range available is not infinite and their n.times.p format (n words each of p bits) is not adaptable to specific cases without an expensive loss of words or bits not used.
An object of the present invention is a read/write memory cell and an arrangement of such cells forming a read/write memory with an n.times.p format (n words each of p bits) especially suited to implementation in free interconnection semi-custom MOS integrated circuit form.
The invention provides for limiting the interconnection network of a free interconnection semi-custom integrated circuit read/write memory to the vertical interconnections, and thus for considering as active, and electrically live, the entire surface area of the integrated circuit. Furthermore, the implementation of a read/write memory cell in accordance with the invention requires only eight transistors (four of type P and four of type N) which, given the organisation of the transistors in a free interconnection semi-custom type integrated circuit, ensures compact dimensions in association with high capacity.
Also, the fact that each cell in accordance with the invention requires only two control signals, whether for writing or reading or in the absence of any write or read operation, authorizes matrix-type addressing and, given a matrix arrangement of a set of such cells to form a memory with an n.times.p format (n words each of p bits), offers the possibility of expanding the memory by simple repetition, without major modification of the structure and thus of the fabrication process.